Semiconductor device and method of providing regions of low substrate capacitance

ABSTRACT

A semiconductor device ( 2 ) includes a semiconductor substrate ( 12 ) having a surface ( 13 ) formed with a first recessed region ( 20 ). A first dielectric material ( 60 ) is deposited in the first recessed region and formed with a second recessed region ( 76 ), and a second dielectric material ( 100 ) is grown over the first dielectric material to seal the second recessed region.

BACKGROUND OF THE INVENTION

[0001] The present invention relates in general to semiconductor devicesand, more particularly, to integrated circuits having components formedon a low capacitance region of a semiconductor die.

[0002] Semiconductor technology continues to scale transistors to havesmaller dimensions in order to provide increased functionality and ahigher frequency capability. For example, wireless communication devicesoften use integrated circuits that include high-density digital signalprocessing functions on the same die as analog circuits operating atfrequencies in excess of five gigahertz.

[0003] However, some integrated circuit components, such as passivedevices, are not readily scalable. These devices have relatively highparasitic substrate capacitances, which often limits the overallfrequency capability of an integrated circuit. For example, inductorsare not easily reduced in size without reducing their quality factor orinductance to an unacceptable level, and bonding pads are not scalablebecause of the need to attach wire bonds to the bonding pads.

[0004] A variety of techniques have been tried to reduce the parasiticcapacitances of passive integrated circuit components. One suchtechnique is to form the components over a low permittivity material.However, current low permittivity materials are limited to filmthicknesses that are too thin to produce a substantial reduction inparasitic capacitance. Another approach is to form the components over athick dielectric film in which are formed air gaps or voids that reducethe overall permittivity of the dielectric film. Previously, voids wereformed using thermally grown dielectric films to form the trench, anddeposited films to seal them. However, voids made with such filmsintroduce substantial stress in a semiconductor substrate, whichdegrades the performance and reliability of the integrated circuit.Also, these voids are not optimized for reducing capacitance due to therelatively high dielectric constant of the films used to form them.Furthermore, the voids are filled with these films during the sealingprocess producing a void with increased dielectric constant. Otherschemes reduce the stress by producing fewer voids or voids with only alimited volume, which has a correspondingly limited effect on parasiticcapacitance. Moreover, in order to avoid contaminating the transistorsor reducing the die yield or reliability, complex and costly schemes arerequired to enable the integration of the low permittivity structureswith active devices such as transistors.

[0005] Hence, there is a need for a low capacitance structure and methodof making an integrated circuit that maintains a low cost while reducingdie stress and avoiding the introduction of contaminants into theintegrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a cross-sectional view of an integrated circuit after afirst fabrication stage;

[0007]FIG. 2 is a cross-sectional view of the integrated circuit after asecond fabrication stage;

[0008]FIG. 3 is a cross-sectional view of the integrated circuit after athird fabrication stage;

[0009]FIG. 4 is a cross-sectional view of the integrated circuit after afourth fabrication stage;

[0010]FIG. 5 is a top view of the integrated circuit after the fourthfabrication stage; and

[0011]FIG. 6 is a cross-sectional view of the integrated circuit after afifth fabrication stage.

DETAILED DESCRIPTION OF THE DRAWINGS

[0012] In the figures, elements having the same reference number havesimilar functionality.

[0013]FIG. 1 is a cross-sectional view of an integrated circuit orsemiconductor device 2 formed with a semiconductor substrate 12 after afirst processing stage.

[0014] Semiconductor substrate 12 includes a base layer 10 formed tohave a thickness of about two hundred and fifty micrometers. In oneembodiment, base layer 10 is heavily doped to have a p-type conductivityand a resistivity of about 0.01 ohm-centimeters to function as a groundplane for integrated circuit 2. In one embodiment, base layer 10comprises monocrystalline silicon.

[0015] An epitaxial layer 30 is grown to a thickness of about threemicrometers over base layer 10. In one embodiment, epitaxial layer 30comprises monocrystalline silicon doped to have a p-type conductivityand a resistivity of about twenty ohm-centimeters.

[0016] A dielectric layer 40 is formed over epitaxial layer 30 to athickness of about three hundred Angstroms to form a hard mask. In oneembodiment, dielectric layer 40 is formed with a thermally grown silicondioxide.

[0017] A dielectric layer 50 is formed over dielectric layer 40. In oneembodiment dielectric layer 50 is formed with plasma enhanced chemicalvapor deposition (PECVD) tetra-ethyl-ortho-silicate (TEOS) glass as ablanket silicon dioxide to a thickness of about three thousandAngstroms.

[0018] A surface 13 of substrate 12 is patterned with photoresist tomask a series of standard etch steps that remove exposed portions ofdielectric layer 40 and dielectric layer 50. A standard anisotropicsilicon etch is then applied to remove exposed portions of epitaxiallayer 30 and base layer 10 to concurrently form recessed region ortrench 20 within an isolation region 22, and recessed region or trench21 around an active device region 145. Isolation region 22 is forforming electrical components such as passive devices and bonding pads,and active region 145 for forming transistors and other active devices.

[0019] Recessed regions 20 and 21 typically are formed concurrently andwith the same processing steps. However, in order to accommodatepotentially different isolation requirements of active device regions ascompared to passive component isolation regions, recessed region 20within isolation region 22 and recessed region 21 around active deviceisolation area 145 may have different vertical and lateral dimensions,although processed using the same fabrication steps. In one embodiment,recessed region 20 in is formed to a depth of about five micrometers anda width of about three micrometers. In one embodiment, recessed region21 is formed to a depth of about five micrometers and a width of abouttwo micrometers.

[0020]FIG. 2 shows a cross-sectional view of integrated circuit 2 aftera second fabrication stage. A standard wet chemistry etch is used toclean the recessed region 20, and during this clean TEOS dielectriclayer 50 is removed and some of the dielectric layer 40 is removedleaving a portion 45 of dielectric layer 40 as shown.

[0021] In one embodiment, a dielectric layer (not shown) is formed inrecessed region 20 over sidewalls 31 of epitaxial layer 30 to athickness of about three hundred Angstroms to promote adhesion ofsubsequent layers to the epitaxial layer.

[0022] A dielectric material 60 is then deposited onto substrate 12covering the substrate and filling recessed region 20. In oneembodiment, dielectric material 60 is silicon dioxide formed with PECVDTEOS deposited at a temperature of about three hundred and fifty degreescentigrade for about thirty minutes. Dielectric material 60 typicallyhas a dielectric constant of about 3.5 and is formed to a thickness ofabout 4.5 micrometers, filling recessed region 20 above dielectric layer45.

[0023] Deposited dielectrics such as dielectric material 60 have severaladvantages over thermally grown films or silicon. For example, thickdielectric films are formed quickly and at low temperatures, havereduced stress, a minimal impact on the overall thermal budget, lowcost, and fast etching characteristics. In addition, the dielectricconstants typically are lower than many other films or materials used toform low dielectric structures.

[0024] Dielectric material 60 is then subjected to a blanket, timed etchto remove a predetermined thickness, leaving dielectric material withinrecessed region 20 to a level below dielectric layer 45. In oneembodiment, the dielectric material etch back process is performed usingreactive ion-etch to a distance 48 below surface 46 to define thethickness of materials deposited in recessed region 20 as described indetail below. In one embodiment, the dielectric material 60 is etchedback so that distance 48 is approximately 0.5 micrometers below surface46.

[0025] A material 70 is deposited onto the substrate 12, covering thesurface of substrate 12 and filling trench 20 above dielectric layer 45.In one embodiment, the material 70 is formed with chemical vapordeposition (CVD) polysilicon at a temperature of about six-hundred andtwenty five degrees centigrade and a thickness of about four-thousandfive-hundred Angstroms for about forty-five minutes.

[0026]FIG. 3 shows a cross-sectional view of integrated circuit 2 aftera third fabrication stage. A standard planarizing etch is performedusing dielectric layer 45 as an etch stop. A photo mask layer 80 isapplied over the material and used to pattern an etch that removesexposed portions of layer 70 and stops on dielectric material 60 to forma cap layer 75.

[0027] In one embodiment, a compression layer (not shown) comprising CVDsilicon nitride at a temperature of about seven hundred eighty degreescentigrade for about eighty minutes to a thickness of about two thousandAngstroms is deposited on top of cap layer 75. When oxidized, thiscompression layer provides additional lateral expansion of cap layer 75as a means to seal larger recessed regions during later processing,although for smaller recessed regions this compression layer may not berequired.

[0028]FIG. 4 shows a cross-sectional view of integrated circuit 2 aftera fourth fabrication stage. Photo mask layer 80 is removed. An etch isperformed to remove the dielectric material 60 to a depth 91 of aboutfour and one-half micrometers to form a recessed region or trench 76that define an array of pillars 65. In one embodiment, the etch isformed using reactive ion etching at a temperature of aboutthree-hundred and fifty degrees centigrade, a pressure of about 250millitorr, a power of about 1500 watts using the gases sulfurhexafluoride and oxygen until the material is cleared from the bottom 93of the trench 76.

[0029] A dielectric material 95 is deposited onto walls 92 to providereinforcement for additional stability under stress and to reducedefects. In one embodiment, dielectric material 95 is formed having adielectric constant of about 11.8 using CVD polysilicon deposited at atemperature of about six-hundred and fifty degrees centigrade for aboutfive minutes to a thickness of about five-hundred Angstroms. In anotherembodiment, dielectric material 95 is formed with amorphous siliconhaving a dielectric constant of about 11.8 to a thickness of aboutfive-hundred Angstroms using chemical vapor deposition performed at atemperature of about five-hundred fifty degrees centigrade for abouttwenty-five minutes.

[0030] In an embodiment where recessed region 20 has a small area sostability and defects are less critical, the pillar reinforcementprocess described above can be left out to reduce costs.

[0031]FIG. 5 is a top view of integrated circuit 2 showing features ofisolation region 22 and active region 145 after the processing stagedescribed in FIG. 4. Trench 76 surrounds and effectively defines activeregion 145 as shown, and within isolation region 22 form a matrix orgrid to define pillars 65. As will be apparent from the subsequentprocessing steps, a variety of alternate arrangements can be used toform the trench 76. For example, an array of holes could be etched toform trench 76, effectively reversing the positions of pillars 65 andtrench 76. That is, pillars 65 can be formed as a contiguous matrixwhile trench 76 are etched as an array of discrete holes. Alternatively,trench 76 may be formed as a series of parallel trenches or recessedregions within isolation region 22. Furthermore, while pillars 65 areshown having a generally rectangular shape, pillars 65 can be of othershapes including generally oval, generally reticulated, and generallyelongated.

[0032]FIG. 6 shows a cross-sectional view of integrated circuit 2 aftera fifth fabrication stage. Recall that cap layer 75 is formed withpolysilicon, which now is thermally oxidized at a temperature of aboutone thousand degrees centigrade to form a dielectric material 100 thatseals openings of trench 76 to form voids 200. In one embodiment,dielectric material 100 is formed with a dielectric constant of about3.8 to a thickness of approximately 0.2 micrometers above EPI layer 30.Depending on the dimensions of the trench 76, some of the siliconmaterial 175 of cap layer 75 may not be converted to silicon dioxide.For example, if the dimensions are suitable and a shorter oxidation stepis desired, complete oxidation of cap layer 75 is not needed to sealrecessed region 76. Note that by thermally oxidizing cap layer 75 toproduce the dielectric material 100 sealing the openings of the trench76, the invention avoids the problem of prior art in which void sealingmaterial is also substantially deposited into the trench resulting invoids with less gaseous volume, thus higher dielectric constant.

[0033] Dielectric material 100 is patterned and/or removed in the activeregion and an active device 140 such as an n-channelmetal-oxide-semiconductor field-effect transistor is formed as follows.A dielectric material is thermally grown over epitaxial layer 30 and apolysilicon material is deposited over the dielectric material. Thepolysilicon and dielectric materials are patterned and etched to form agate dielectric 143 and an overlying gate electrode 144 of transistor140 as shown. Gate dielectric 143 and gate electrode 144 are used incombination with a photoresist layer (not shown) to form a mask forintroducing n-type dopants into epitaxial layer 30 to form aself-aligned source 141 and drain 142 of transistor 140. In oneembodiment, source 141 and drain 142 are heavily doped and formed to adepth of about one-half micrometer.

[0034] The region between the pillars 90 that have been sealed off toproduce voids 200 are so designated because they are filled with agaseous material, which in one embodiment may be air. Voids 200 may alsobe filled with argon or another ambient gas that is present when thetrench 76 become sealed off.

[0035] Note that voids 200 are formed early in the process, i.e., beforetransistor 140 is formed. For some processes required to form transistor140 it may be advantageous to leave the step of sealing as describedabove until the gate dielectric 143 formation such that any concerns ofgases trapped in the voids are eliminated, or to accommodate thetransistor thermal processing budget. The simple process described aboveis compatible with standard semiconductor processing, has a low thermalbudget, and can be implemented at virtually any point of an activedevice fabrication process.

[0036] Dielectric material is deposited on substrate 12 and planarizedto re-form the layer 100 as shown in FIG. 6. Dielectric material 100 mayalso function as an interlayer dielectric that separates metallizationinterconnect layers.

[0037] The effective dielectric constant of isolation region 22 is acombination of the dielectric constant or permittivity of voids 200 andthe permittivity of the material used to form the pillars 65, anddielectric material 100. In one embodiment, the gaseous materialcontained in voids 200 has a dielectric constant substantially equal toone, and the wall reinforcement material 95 has a dielectric constant ofabout 3.8, thus the overall dielectric constant of the isolation regionformed is less than 3.8, depending on the relative volumes of pillars65, reinforcement material 95, and voids 200. Thus, the invention avoidsthe problem of prior art in which the isolation region 22 is comprisedof gas, dielectric material, and semiconductor material thus producing aisolation region having a correspondingly higher dielectric constant.Hence, isolation region 22 has a low effective permittivity for formingelectrical components with a low parasitic substrate capacitance.

[0038] An electrical component 120 is formed on dielectric material 100over isolation region 22. Electrical component 120 has a low parasiticcapacitance to substrate 12, and therefore a higher frequencycapability, because of the low permittivity of isolation region 22.Electrical component 120 may be a bonding pad, a passive component suchas an inductor, capacitor or resistor, or another electrical devicesuitable for formation over a dielectric material.

[0039] In summary, the present invention provides a semiconductor devicecomprising a semiconductor substrate having a surface formed with afirst recessed region; a first dielectric material deposited in thefirst recessed region and formed with a second recessed region; and asecond dielectric material grown over the first dielectric material toseal the second recessed region.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate having a surface formed with a first recessedregion; a first dielectric material deposited in the first recessedregion and formed with a second recessed region; and a second dielectricmaterial thermally grown over the first dielectric material to seal thesecond recessed region.
 2. The semiconductor device of claim 1, furthercomprising an active device formed in an active region of thesemiconductor substrate.
 3. The semiconductor device of claim 1, furthercomprising an electrical component formed over the second recessedregion.
 4. The semiconductor device of claim 3, wherein the electricalcomponent comprises a passive device or bonding pad of the semiconductordevice.
 5. The semiconductor device of claim 1, wherein thesemiconductor substrate is formed with silicon.
 6. The semiconductordevice of claim 1, wherein the first dielectric material includesdeposited silicon dioxide.
 7. The semiconductor device of claim 1,wherein the second recessed region is formed having a third dielectricmaterial deposited on the walls.
 8. The semiconductor device of claim 1,wherein the second dielectric material is formed with thermally grownsilicon dioxide.
 9. The semiconductor device of claim 1, wherein thefirst dielectric material includes a cap layer.
 10. The semiconductordevice of claim 9, wherein the cap layer includes a chemical vapordeposition film.
 11. The semiconductor device of claim 1, where thesecond recessed region extends into the semiconductor substrate to thedepth of at least five micrometers.
 12. A method of making asemiconductor device, comprising the steps of: masking a material toform dielectric pillars in a recessed region; and oxidizing a cap layerto form a seal over regions between the dielectric pillars.
 13. Themethod of claim 12 wherein the material is formed with deposited silicondioxide.
 14. The method of claim 12, wherein the step of masking furthercomprises the steps of: depositing the cap layer over the semiconductormaterial; removing portions of the cap layer to expose the underlyingsemiconductor material; and etching the exposed underlying semiconductormaterial to form the dielectric pillars.
 15. The method of claim 14,wherein the cap layer is formed with chemical vapor deposition film. 16.The method of claim 12, wherein the step of oxidizing includes the stepof thermally growing silicon dioxide.
 17. The method of claim 12 furthercomprising the step of forming an electrical component over regionsbetween the dielectric pillars after the step of oxidizing the caplayer.
 18. The method of claim 17 wherein the electrical componentcomprises a passive device or bonding pad of the semiconductor device.19. The method of claim 12, wherein the step of oxidizing is performedafter the step of depositing a dielectric onto the walls of the pillars20. The method of claim 19 wherein the dielectric includes chemicalvapor deposition film.
 21. The method of claim 12, further comprisingthe step of forming an active device in an active region of thesemiconductor device after the step of oxidizing the cap layer.
 22. Amethod of fabricating an integrated circuit, comprising the steps of:etching a first dielectric material deposited within a recessed regionto form dielectric pillars; growing a second dielectric material to forma seal over the dielectric pillars; and forming a passive component overthe second dielectric material.
 23. The method of claim 22, furthercomprising the step of depositing a semiconductor material over thedielectric pillars prior to the step of etching the first dielectricmaterial.
 24. The method of claim 23, wherein the step of growing asecond dielectric material includes the step of oxidizing thesemiconductor material.
 25. The method of claim 22, wherein the passivecomponent includes a bonding pad.